Apparatus for maintaining consistency of a cache memory with a primary memory

Patent 4933835 Issued on June 12, 1990. Estimated Expiration Date:

January 19, 2009. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

3693765

3723976

3761881

3764996

3896419

3898624

3902164

Memory system with parallel access to multi-word blocks
Patent #: 3956737
Issued on: 05/11/1976
Inventor: Ball

Data processing system for converting from logical addresses to physical addresses
Patent #: 4037209
Issued on: 07/19/1977
Inventor: Nakajima , et al.

Address translation system
Patent #: 4057848
Issued on: 11/08/1977
Inventor: Hayashi

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Inventors

Assignee

Intergraph Corporation

Application

No. 300174 filed on 01/19/1989

US Classes:

711/123User data cache and instruction data cache

Examiners

Primary: Zache, Raulfe B.
Assistant: Mills, John G.

Attorney, Agent or Firm

Townsend and Townsend

Foreign Patent References

58-58666 JP 04/13/1983
60-41146 JP. 03/13/1985
60-120450 JP. 06/13/1985
60-144847 JP. 07/13/1985
1444228 GB 07/13/1976

International Class

G06F 009/00

Abstract

A microprocessor system is disclosed having a high speed system bus for coupling system elements, and having a dual bus microprocessor with separate ultra-high speed instruction and data cache-MMU interfaces coupled to independently operable instruction and data cache-MMU, respectively. A main memory is coupled to the system bus for selectively storing and outputting digital information. The instruction and data cache-MMU's are coupled to the main memory via the system bus for independently storing and outputting digital information to respective mapped addressable very high speed cache memory. The microprocessor is coupled via separate and independent very high speed instruction and data buses to each of the instruction cache-MMU and data cache-MMU, respectively, for processing data received from the data cache-MMU responsive to instructions received from the instruction cache-MMU. The instruction bus and data bus are exclusive and independent of one another, and allow for simultaneous very high-speed transfer. The data cache-MMU and instruction cache-MMU each have separate dedicated system bus interfaces for coupling to the main memory and to other peripheral devices which are coupled to the system bus. Numerous other system elements can also be coupled to the system bus, including an interrupt controller, an I/O processor, a bus arbiter, an array processor, and other peripheral controller devices.

Other References

Losq, et al., "Conditional Cache Miss Facility for Handling Short/Long Cache Requests", IBM TDB, vol. 25, No. 1, Jun. '82, pp. 110-111
MC68120/MC68121--Intelligent Peripheral Controller Users Manual, Motorola, Inc
Electronics International, vol. 55, No. 16, Aug. 1982, pp. 112-117, N.Y., 115; P. Knudsen: "Supermini Goes Multiprocessor Route to Put it up Front in Performance