Multiprocessor/memory interconnection network wherein messages sent through the network to the same memory are combined
Patent 4920484 Issued on April 24, 1990. Estimated Expiration Date: 
October 5, 2008. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
October 5, 2008. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesShared memory computer method and apparatus Collision avoidance apparatus File transfer scheduling arrangement Idle period signalling in a packet switching system Delta network of a cross-point switch Pipeline feedback array sorter with multi-string sort array and merge tree array Patent #: 4799152 InventorApplicationNo. 253961 filed on 10/05/1988US Classes:709/245, COMPUTER-TO-COMPUTER DATA ADDRESSING340/2.6, Plural stages340/825.02, Tree or cascade370/415, Having input queuing only709/246COMPUTER-TO-COMPUTER DATA MODIFYINGExaminersPrimary: Smith, JerryAssistant: Kulbaski, James J. Attorney, Agent or FirmInternational ClassesG06R 013/00H04Q 011/04 AbstractA method and apparatus is described for enabling efficient, bilateral communications in a network connecting a plurality of target address modules and a plurality of source address generators. The source address generators are enabled to generate requests to target addresses within the target address modules. The function of the network is to forward the requests to the target address modules holding the respective target addresses and to return the replies generated by the target address module to the respective source address generators. The network interconnects the source generators to each target address module and vice versa. The interconnection network includes a plurality of interconnected nodes, each node having M inputs and N outputs (where M may or may not be equal to N) and a processor for carrying out a communication protocol. The protocol comprises each node first placing incoming target addresses from messages appearing on the node's inputs into a queue associated with each respective input. The target addresses of the messages at the head of each queue are examined, and the message is transmitted whose target address bears a predetermined relationship to the other message's target address. The messages are combined in case their target addresses are found to be equal. Additionally, a direction bit queue is provided in which is stored a sequence of bits indicating from which of the M inputs to the node, the transmitted message was received. A "ghost" message is transmitted (which includes the target address of the message transmitted) on the node's other outputs, to notify interconnected nodes of the transmitted target address. In addition, each source address generator periodically generates an "end of stream" message.Other References
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