High temperature interconnect system for an integrated circuit
Patent 4920071 Issued on April 24, 1990. Estimated Expiration Date: August 18, 2007. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
438/626, Planarization257/E21.58, Planarizing dielectric (EPO)257/E21.585, Filling of holes, grooves, vias or trenches with conductive material (EPO)257/E21.589, By forming conductive members before deposition of protective insulating material, e.g., pillars, studs (EPO)257/E23.163, Principal metal being refractory metal (EPO)438/627, At least one layer forms a diffusion barrier438/632, Utilizing reflow438/643At least one layer forms a diffusion barrier
A semiconductor integrated circuit device is provided with an electrical interconnect system which is stable at high temperatures. The interconnect system employs refractory metal compounds which are electrically conductive, which form stable couples with silicon and compounds thereof, and which remain stable at temperatures exceeding approximately 500° C.
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