Adder cell having a sum part and a carry part
Patent 4918640 Issued on April 17, 1990. Estimated Expiration Date: 
January 12, 2009. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
January 12, 2009. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesLogic operation circuit having an exclusive-OR circuit Full adder circuit using differential transistor pairs Full adder circuit having an exclusive-OR circuit Patent #: 4831579 InventorsAssigneeApplicationNo. 296070 filed on 01/12/1989US Classes:708/670, Addition/subtraction326/38, Having details of setting or programming of interconnections or logic functions326/41, Significant integrated structure, layout, or layout interconnections708/701Bipolar junction transistor only or combined with Field-Effect TransistorExaminersPrimary: Miller, Stanley D.Assistant: Wambach, Margaret Rose Attorney, Agent or FirmInternational ClassesG05F 007/50H03K 017/16 Foreign Application Priority Data1988-02-05 DEAbstractAn adder cell having a sum part and a carry part, whereby the sum part and the carry part each contain differential amplifiers having exclusively bipolar or ECL technology as well as differential amplifiers having mixed bipolar MOS transistors. The processing speed can be considerably increased with such an arrangement in comparison to exclusive CMOS adder cells. Additionally, the adder cell carries out a level conversion of CMOS input levels to ECL output levels, so that CMOS levels between 0 and 5 volts can be received at the first four inputs (E1, E2, E3, E4) and ECL boosts in the millivolt range can be taken at the sum outputs (S, S) or, at the carry outputs (CO, CO).Other References
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