TDM bus controller
March 14, 2008. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3856993 Decentralized data transmission system Bus allocation synchronization system Speech and data communication network Bimodal bus accessing system Local network interface with control processor & DMA controller for coupling data processing stations to common serial communications medium Common bus access system using plural configuration tables for failure tolerant token passing among processors Control channel interface circuit Multi-processor system with communication controller using poll flags for non-contentious slot reservation High performance dynamic sense amplifier with dual channel grounding transistor Inventors
AssigneeApplicationNo. 167816 filed on 03/14/1988US Classes:370/451On busExaminersPrimary: Olms, Douglas W.Assistant: Marcelo, Melvin Attorney, Agent or FirmInternational ClassH04J 003/24AbstractAn apparatus for controlling access to a time division multiplexed (TDM) bus includes a frame address register having a plurality of storage registers for storing a plurality of frame addresses designated for use in communicating over said TDM bus. A frame address latch stores a current frame address. A frame comparator, coupled to the frame address register and the frame address latch, compares the designated frame addresses with the current frame address and produces a first signal indicative of the storage register containing a frame address matching the current frame address. A time slot register has a plurality of storage registers for storing a time slot number designated for use in communicating over said TDM bus. A time slot generator generates a current time slot number. A time slot comparator, coupled to the time slot register and the time slot generator compares the designated time slot number with the current time slot number and produces a second signal indicative of the storage register containing a slot number matching the current time slot number. A token generator, coupled to the frame comparator and the time slot comparator receives the first and second signals and generates a token work unique to the first and second signals. A data transfer circuit transfers a data word to or from the TDM bus responsive to the token word. | |
