Adder using multi-state logic
August 24, 2008. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesBinary adder circuit Fast, efficient, small adder CMOS full adder circuit Highspeed parallel adder with clocked switching circuits Logic operation circuit having an exclusive-OR circuit Logic arithmetic circuit Full adder circuit using differential transistor pairs Full adder circuit having an exclusive-OR circuit Patent #: 4831579 InventorsAssigneeApplicationNo. 235528 filed on 08/24/1988US Classes:708/701, Bipolar junction transistor only or combined with Field-Effect Transistor708/707Carry-rippleExaminersPrimary: Clark, David L.Assistant: Mai, Tan V. Attorney, Agent or FirmInternational ClassG06F 007/50Foreign Application Priority Data1987-08-28 JPAbstractA binary digital full adder as a component element of a digital circuit receives three binary signals including two input signals and a carry-in from the lower digit. The adder comprises a four-state logic converter for adding together the three binary signals in terms of current addition to convert the sum into a four-state logic signal, and an encoder for deciding a four-state logic level to encode it into a binary sum and a carry-out. | |
