Semiconductor package
May 30, 2009. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3842492 Flat package for integrated circuit devices Process of making multi-layer ceramic package Semiconductor arrangement with connector conductors cut out of sheetmetal Wire bonds and electrical contacts of an integrated circuit device Support assembly for integrated circuits High packing density lead frame and integrated circuit Metal electronic package sealed with thermoplastic having a grafted metal deactivator and antioxidant Direct current sense lead Resin packaged semiconductor device having a protective layer made of a metal-organic matter compound InventorApplicationNo. 358992 filed on 05/30/1989US Classes:257/666, LEAD FRAME257/784, Wire contact, lead, or bond257/786, Configuration or pattern of bonds257/787, ENCAPSULATED257/E23.031Lead frames or other flat leads (EPO)ExaminersPrimary: James, Andrew J.Assistant: Pemrick, James W. Attorney, Agent or FirmInternational ClassH01L 023/48AbstractIn an encapsulated semiconductor module in which a semiconductor chip, having a major surface with terminals thereon, is deposed within the encapsulating material, a plurality of self-supporting, unitary, discrete, and continuous lead frame conductors formed of metal sheet stock are positioned at various locations around the chip and cantilevered out of the encapsulating material, so that discrete wires can be used to connect respective ones of said conductors to respective ones of said terminals. In the present invention excessively long bonding wires are avoided by connecting a selected one of said lead frame conductors to a parallel conductor by a jumper wire and connecting the parallel conductor to the desired terminal with a short wire.Other References
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