Abstract

A modular and hierarchical multiple bus computer architecture in which the master bus and slave bus are substantially identical, and communicate through a combination of an interface controller and a shared dual port RAM responsive to a shared RAM controller. Processor engine modules including a bus, a processor, an interface controller, a shared dual port RAM, and a shared RAM controller are horizontally and/or vertically integrated at multiple levels without major restructuring of the composite system control operations by having each slave processor engine module interface as a peripheral upon the bus of its master. The modularity of the architecture allows the use of standard peripherals and platform processor engines to expand memory or increase functionality without burdening the master bus processor engine. Each slave bus processor engine is fully functional as an independent processor with mastery over its own bus. The architecture is particularly efficient in extended data base, fault tolerant data base or multi-communication system adapter interface functions.