U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Parallel data processor

Patent 4908751 Issued on March 13, 1990. Estimated Expiration Date: Icon_subject October 15, 2007. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Image processor
Patent #: 4601055
Issued on: 07/15/1986
Inventor: Kent

Matrix-matrix multiplication using an electrooptical systolic/engagement array processing architecture
Patent #: 4603398
Issued on: 07/29/1986
Inventor: Bocker ,   et al.

Data processing system having a pyramidal array of processors
Patent #: 4622632
Issued on: 11/11/1986
Inventor: Tanimoto ,   et al.

Advanced cube processor
Patent #: 4633427
Issued on: 12/30/1986
Inventor: Bocker

Image processor
Patent #: 4635292
Issued on: 01/06/1987
Inventor: Mori ,   et al.

Digital data processor incorporating an orthogonally connected logic cell array
Patent #: 4639857
Issued on: 01/27/1987
Inventor: McCanny ,   et al.

Multiprocessor system employing dynamically programmable processing elements controlled by a master processor
Patent #: 4641238
Issued on: 02/03/1987
Inventor: Kneib

Memory-linked wavefront array processor
Patent #: 4720780
Issued on: 01/19/1988
Inventor: Dolecek

Image preprocessing by modified median filter
Patent #: 4736439
Issued on: 04/05/1988
Inventor: May

Geometric-arithmetic parallel processor
Patent #: 4739474
Issued on: 04/19/1988
Inventor: Holsztynski

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Inventor

Application

No. 108774 filed on 10/15/1987

US Classes:

712/12, Cube or hypercube382/304, Parallel processing708/816Optical

Examiners

Primary: James, Andrew J.
Assistant: Nguyen, Viet Q.

International Classes

G06F 013/00
G06K 009/56
G06G 009/00

Abstract

A data processing system for simultaneously processing a plurality of data words, comprising one or more data processing planes each of which comprises a plurality of processing entities logically organized as rows and columns as a two dimensional array of processing entities, each of the processing entities being operable for performing arithmetic and logical operations on data words in a substantially simultaneous manner with others of the processing entities. Substantially all of the processing entities are operatively coupled to at least one other processing entity in an immediately adjacent row or column for transferring data therebetween and are also further operatively coupled to at least one other processing entity in a nonadjacent row or column for transferring data therebetween.

Other References

  • Dick Poutain, "A Personal Transputer", Byte, Jun./88, pp. 303-308
  • "Convolution Hardware Accelerates Imaging Tasks" D. MacRae, Electronic System Design Magazine, Jan. 1987, pp. 58-62
  • "The Connection Machine" by W. Daniel Hillis, Scientific America, Jun. 1987, pp. 108-115
  • "Warp Project Spawning Computers Based on Systolic Processing" by Chappell Brown, Electronic Engineering Times, Jun. 1, 1987, pp. 33,36
  • Device Specification: AM95c85 Content Addressable Data Manager, 9/85
  • Product Specification "The Transputer Family" Inmos Corp., 6/86, 3/8
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