U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Integrated dual charge pump power supply and RS-232 transmitter/receiver

Patent 4897774 Issued on January 30, 1990. Estimated Expiration Date: Icon_subject November 14, 2008. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

3470443

3731112

3878450

MOS DC Voltage booster circuit
Patent #: 3942047
Issued on: 03/02/1976
Inventor: Buchanan

DC to DC Voltage converter
Patent #: 3943428
Issued on: 03/09/1976
Inventor: Whidden

Direct current power converters employing digital techniques used in electronic timekeeping apparatus
Patent #: 3955353
Issued on: 05/11/1976
Inventor: Astle

Capacitive voltage converter employing CMOS switches
Patent #: 3975671
Issued on: 08/17/1976
Inventor: Stoll

Capacitive voltage multiplier
Patent #: 4047091
Issued on: 09/06/1977
Inventor: Hutchines ,   et al.

Circuit for obtaining DC voltage higher than power source voltage
Patent #: 4061929
Issued on: 12/06/1977
Inventor: Asano

Voltage multiplier for an electronic time apparatus
Patent #: 4068295
Issued on: 01/10/1978
Inventor: Portmann

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Inventors

Assignee

Application

No. 271160 filed on 11/14/1988

US Classes:

363/61, For rectifying307/110Parallel-charge, series-discharge (e.g., voltage doublers)

Examiners

Primary: Salce, Patrick R.
Assistant: Jones, Judson H.

Attorney, Agent or Firm

Foreign Patent References

  • 0080264 JP 05/12/1982
  • 0951602 SU 08/12/1982

International Class

002M 007/25

Abstract

A monolithic integrated circuit containing an inverting/non-inverting voltage doubler charge pump circuit is disclosed for converting a unipolar supply voltage to a bipolar supply voltage of a greater magnitude. The unipolar input voltage is placed across a first external transfer capacitor by a first set of MOS switches during a first time period. The unipolar input voltage source is placed in series with the first transfer capacitor and this series combination of voltages is placed across a first external reservoir capacitor by a second set of MOS switches during a second time period. The voltage appearing across the first external reservoir capacitor is placed on a second transfer capacitor during the first time period by a third set of MOS switches. The voltage across the second transfer capacitor is placed into a second external reservoir capacitor with its polarity inverted by a fourth set of MOS switches during the second time period. A dual-collector lateral junction transistor, formed during the conventional CMOS processing steps used to fabricate the MOS switches, is connected as a voltage clamp between a ground potential and the two bipolar DC output lines of the power supply circuit to assure correct start-up conditions for the circuit. Gain reduction devices are placed in the semiconductor substrate to collect minority carriers which would otherwise be injected into inherent parasitic four layer PNPN junction devices created as a result of the architecture of the circuit, to prevent latch-up of the four layer devices. In a preferred embodiment, an RS-232 receiver and transmitter are contained on the same monolithic integrated circuit as the dual charge pump power supply.

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