Patent References 3470443 3731112 3878450 MOS DC Voltage booster circuit DC to DC Voltage converter Direct current power converters employing digital techniques used in electronic timekeeping apparatus Capacitive voltage converter employing CMOS switches Capacitive voltage multiplier Circuit for obtaining DC voltage higher than power source voltage Voltage multiplier for an electronic time apparatus InventorsAssigneeApplicationNo. 271160 filed on 11/14/1988US Classes:363/61, For rectifying307/110Parallel-charge, series-discharge (e.g., voltage doublers)ExaminersPrimary: Salce, Patrick R.Assistant: Jones, Judson H. Attorney, Agent or FirmForeign Patent References
International Class002M 007/25AbstractA monolithic integrated circuit containing an inverting/non-inverting voltage doubler charge pump circuit is disclosed for converting a unipolar supply voltage to a bipolar supply voltage of a greater magnitude. The unipolar input voltage is placed across a first external transfer capacitor by a first set of MOS switches during a first time period. The unipolar input voltage source is placed in series with the first transfer capacitor and this series combination of voltages is placed across a first external reservoir capacitor by a second set of MOS switches during a second time period. The voltage appearing across the first external reservoir capacitor is placed on a second transfer capacitor during the first time period by a third set of MOS switches. The voltage across the second transfer capacitor is placed into a second external reservoir capacitor with its polarity inverted by a fourth set of MOS switches during the second time period. A dual-collector lateral junction transistor, formed during the conventional CMOS processing steps used to fabricate the MOS switches, is connected as a voltage clamp between a ground potential and the two bipolar DC output lines of the power supply circuit to assure correct start-up conditions for the circuit. Gain reduction devices are placed in the semiconductor substrate to collect minority carriers which would otherwise be injected into inherent parasitic four layer PNPN junction devices created as a result of the architecture of the circuit, to prevent latch-up of the four layer devices. In a preferred embodiment, an RS-232 receiver and transmitter are contained on the same monolithic integrated circuit as the dual charge pump power supply. | |