Patent References 3481030 3558366 High density/high speed MOS process and device Method for making narrow channel FET Retro-etch process for forming gate electrodes of MOS integrated circuits Submicron patterning without using submicron lithographic technique Self-aligned metal process for field effect transistor integrated circuits Self-aligned metal process for field effect transistor integrated circuits using polycrystalline silicon gate electrodes Fabrication of FETs Field effect semiconductor devices and method of making same InventorAssigneeApplicationNo. 305959 filed on 02/02/1989US Classes:438/289, Doping of semiconductive channel region beneath gate insulator (e.g., adjusting threshold voltage, etc.)257/E21.197, Final conductor layer next to insulator being silicon e.g., polysilicon, with or without impurities (EPO)257/E21.434, With initial gate mask or masking layer complementary to prospective gate location, e.g., with dummy source and drain contacts (EPO)257/E21.443, Using self-aligned punch through stopper or threshold implant under gate region (EPO)438/291, Using channel conductivity dopant of opposite type as that of source and drain438/306, Plural doping steps438/307Using same conductivity-type dopantExaminersPrimary: Chaudhuri, OlikAssistant: Quach, T. N. Attorney, Agent or FirmForeign Patent References
International ClassesH01L 021/265H01L 021/283 H01L 021/316 AbstractA method is disclosed for fabricating submicron silicon gate metal-oxide-semiconductor field effect transistors (MOSFETs) which have threshold and punchthrough implants that are self-aligned to the gate electrode and source and drain regions. A layer of dielectric material (12) is either deposited or grown on the surface of a substrate, and a trench (15), which defines the region of the MOSFET gate electrode, is formed in the dielectric layer. A gate oxide (16) is formed at the exposed substrate at the bottom of the trench, and an implant is performed into the silicon substrate wherever there is gate oxide, but not into the portion of the substrate covered by the original dielectric layer. A layer of polysilicon (20), preferably doped, or another metallic film is then deposited onto the surface. The polysilicon is etched back to the top surface of the dielectric layer, thereby leaving polysilicon in the trench to form the gate electrode (24). The dielectric layer (12) is then etched back preferentially to a thickness approximately equal to the thickness of the gate dielectric, and a high-dose implant is performed through the reduced thickness dielectric layer into the silicon substrate, except for the areas covered by the polysilicon gate to form the source and drain regions (30) of the MOSFET. | |