U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Method of fabricating a submicron silicon gate MOSFETg21 which has a self-aligned threshold implant

Patent 4895520 Issued on January 23, 1990. Estimated Expiration Date: Icon_subject February 2, 2009. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

3481030

3558366

High density/high speed MOS process and device
Patent #: 4033026
Issued on: 07/05/1977
Inventor: Pashley

Method for making narrow channel FET
Patent #: 4212683
Issued on: 07/15/1980
Inventor: Jones ,   et al.

Retro-etch process for forming gate electrodes of MOS integrated circuits
Patent #: 4334348
Issued on: 06/15/1982
Inventor: Trenary ,   et al.

Submicron patterning without using submicron lithographic technique
Patent #: 4358340
Issued on: 11/09/1982
Inventor: Fu

Self-aligned metal process for field effect transistor integrated circuits
Patent #: 4359816
Issued on: 11/23/1982
Inventor: Abbas ,   et al.

Self-aligned metal process for field effect transistor integrated circuits using polycrystalline silicon gate electrodes
Patent #: 4471522
Issued on: 09/18/1984
Inventor: Jambotkar

Fabrication of FETs
Patent #: 4514893
Issued on: 05/07/1985
Inventor: Kinsbron ,   et al.

Field effect semiconductor devices and method of making same
Patent #: 4536782
Issued on: 08/20/1985
Inventor: Brown

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Inventor

Assignee

Application

No. 305959 filed on 02/02/1989

US Classes:

438/289, Doping of semiconductive channel region beneath gate insulator (e.g., adjusting threshold voltage, etc.)257/E21.197, Final conductor layer next to insulator being silicon e.g., polysilicon, with or without impurities (EPO)257/E21.434, With initial gate mask or masking layer complementary to prospective gate location, e.g., with dummy source and drain contacts (EPO)257/E21.443, Using self-aligned punch through stopper or threshold implant under gate region (EPO)438/291, Using channel conductivity dopant of opposite type as that of source and drain438/306, Plural doping steps438/307Using same conductivity-type dopant

Examiners

Primary: Chaudhuri, Olik
Assistant: Quach, T. N.

Attorney, Agent or Firm

Foreign Patent References

  • 0051840 JP 05/13/1981

International Classes

H01L 021/265
H01L 021/283
H01L 021/316

Abstract

A method is disclosed for fabricating submicron silicon gate metal-oxide-semiconductor field effect transistors (MOSFETs) which have threshold and punchthrough implants that are self-aligned to the gate electrode and source and drain regions. A layer of dielectric material (12) is either deposited or grown on the surface of a substrate, and a trench (15), which defines the region of the MOSFET gate electrode, is formed in the dielectric layer. A gate oxide (16) is formed at the exposed substrate at the bottom of the trench, and an implant is performed into the silicon substrate wherever there is gate oxide, but not into the portion of the substrate covered by the original dielectric layer. A layer of polysilicon (20), preferably doped, or another metallic film is then deposited onto the surface. The polysilicon is etched back to the top surface of the dielectric layer, thereby leaving polysilicon in the trench to form the gate electrode (24). The dielectric layer (12) is then etched back preferentially to a thickness approximately equal to the thickness of the gate dielectric, and a high-dose implant is performed through the reduced thickness dielectric layer into the silicon substrate, except for the areas covered by the polysilicon gate to form the source and drain regions (30) of the MOSFET.

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