CMOS implementation of a built-in self test input generator (BISTIG)
Patent 4893311 Issued on January 9, 1990. Estimated Expiration Date: 
April 25, 2008. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
April 25, 2008. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesError detection and correction apparatus for a logic array ROM/PLA Structure and method of testing Random pattern self test design Built in self test input generator for programmable logic arrays Patent #: 4672610 InventorsAssigneeApplicationNo. 185610 filed on 04/25/1988US Classes:714/733, Built-in testing circuit (BILBO)714/736Device response compared to expected fault-free responseExaminersPrimary: Fleming, Michael R.Attorney, Agent or FirmInternational ClassG06F 011/00AbstractA CMOS implementation of a Built In Self Test Input Generator (BISTIG) for testing embedded PLA structures. The BISTIG tests for all stuck at faults, cross-point faults and bridging faults, by asserting exactly one input row and exactly one product term of the PLA under test at a time. | |
