Semiconductor device and a process for manufacturing the same
Patent 4891326 Issued on January 2, 1990. Estimated Expiration Date: 
June 8, 2008. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
June 8, 2008. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod of fabricating an MOS dynamic RAM with lightly doped drain Method of fabricating high speed CMOS devices Method of forming conductive channel extensions to active device regions in CMOS device Patent #: 4530150 InventorAssigneeApplicationNo. 206896 filed on 06/08/1988US Classes:438/228, Plural wells257/321, With thin insulator region for charging or discharging floating electrode by quantum mechanical tunneling257/387, Gate electrode overlaps at least one of source or drain by no more than depth of source or drain (e.g., self-aligned gate)257/408, Including lightly doped drain portion adjacent channel (e.g., lightly doped drain, LDD device)257/412, Gate electrode of refractory material (e.g., polysilicon or a silicide of a refractory or platinum group metal)257/E21.552, Using local oxidation of silicon, e.g., LOCOS, SWAMI, SILO (EPO)257/E21.64, With particular manufacturing method of gate sidewall spacers, e.g., double spacers, particular spacer material or shape (EPO)257/E27.067, Including both N- and P- wells in the substrate, e.g. twin-tub (EPO)257/E29.255, With field effect produced by insulated gate (EPO)438/231Plural doping stepsExaminersPrimary: Wojciechowicz, EdwardAttorney, Agent or FirmForeign Patent References
International ClassesH01L 021/265H01L 029/78 Foreign Application Priority Data1984-05-16 JPAbstractA process for fabricating a semiconductor device having n-channel and p-channel MOSFET's. Each MOSFET has a pair of side walls that are simultaneously formed on both sides of the gate electrode. The n-channel MOSFET has source and drain regions consisting of a low-concentration region formed by implanting ions using the gate electrode as a mask, and a high-concentration region formed by implanting ions using the gate electrode and side walls as masks. The p-channel MOSFET has source and drain regions consisting of high-concentration regions formed by implanting ions using the gate electrode and side walls as masks.Other References
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