U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Process for making a contact structure including polysilicon and metal alloys

Patent 4888297 Issued on December 19, 1989. Estimated Expiration Date: Icon_subject October 20, 2007. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

3496428

3664896

3667008

3833842

3881242

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3906540

Battery snap terminal
Patent #: 4024953
Issued on: 05/24/1977
Inventor: Nailor, III

Method of producing a doped zone of one conductivity type in a semiconductor body utilizing an ion-implanted polycrystalline dopant source
Patent #: 4063967
Issued on: 12/20/1977
Inventor: Graul ,   et al.

Thermal printing head
Patent #: 4096510
Issued on: 06/20/1978
Inventor: Arai ,   et al.

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Inventors

Application

No. 110996 filed on 10/20/1987

US Classes:

438/307, Using same conductivity-type dopant257/E21.166, Conductive layer comprising semiconducting material (EPO)257/E23.019, Consisting of layered constructions comprising conductive layers and insulating layers, e.g., planar contacts (EPO)438/298, Doping region beneath recessed oxide (e.g., to form chanstop, etc.)438/545, Forming partially overlapping regions438/586Combined with formation of ohmic contact to semiconductor region

Examiners

Primary: Hearn, Brian E.
Assistant: Quach, T. N.

Attorney, Agent or Firm

Foreign Patent References

  • 56-111264 JP. 09/13/1981
  • 60-100464 JP. 06/13/1985
  • 2075255 GB. 11/13/1981

International Classes

H01L 021/225
H01L 021/283

Abstract

A multi-layer contact process is described for providing contact to a shallow semiconductor region forming a semiconductor PN junction and with a silicon semiconductor body. The multi-layer structure includes a layer of polycrystalline silicon doped with an impurity of the same conductivity type as that of the semiconductor region. A first layer of a refractory alloy is deposited over the polycrystalline silicon layer to provide electrically stable interface therewith. A second layer of another refractory metal or alloy is deposited over the first refractory metal alloy layer and serves to protect the shallow PN junction against current leakage failure. A third layer of interconnect metal is deposited over the multi-layer contact structure. The resulting structure provides a low resistance ohmic contact to a shallow semiconductor region with improved electrical characteristics.

Other References

  • Shibata et al., IEEE IEDM Technical Digest, 1981, pp. 647-650
  • Osburn et al., IBM Technical Disclosure Bulletin, vol. 24, No. 4, Sept. 1981, pp. 1970-1973
  • Wittmer, M., "High-Temperature Contact Structures for Silicon Semiconductor Devices", Appl. Phys. Lett. 37(6), 15 Sept. 1980, pp. 540-542
  • Lo, T. C., "Self Aligned Contact to a Doped Region", IBM Tech. Disc. Bull., vol. 23, No. 7A, Dec. 1980, pp. 2780-2781
  • Reith, T. M., et al., "Sl/Pts; Schottky Barrier Diodes with a Diffusion Barrier", IBM Tech. Disc. Bull., vol. 16, No. 11, Apr. 1974, p. 3586
  • Ku, S. M., "Ohmic Contacts for Small Shallow Structure Devices", IBM Tech. Disc. Bull., vol. 22, No. 4, Sept. 1979, pp. 1487-1488
  • Babcock, S. E., et al., "Titanium-Tungsten Contacts to Si . . . ", J. Appl. Phys., 53(10), Oct. 1982, pp. 6898-6904
  • Olowolafe, J. O., et al., "Contact Reaction between Si and Pd.W Alloy Films", J. Appl. Phys., 50(10), Oct. 1979, pp. 6316-632
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