Static random access memory with reduced soft error rate
Patent 4879690 Issued on November 7, 1989. Estimated Expiration Date: 
August 11, 2008. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
August 11, 2008. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesData integrity verifying circuit for electrically erasable and programmable read only memory (EEPROM) Patent #: 4811294 InventorsApplicationNo. 231063 filed on 08/11/1988US Classes:365/201, Testing365/189.07, Including signal comparison365/203, Precharge365/208, Semiconductors714/718Memory testingExaminersPrimary: Fears, Terrell W.Attorney, Agent or FirmForeign Patent References
International ClassG11C 013/00Foreign Application Priority Data1987-09-07 JPAbstractA storage node in each of memory cells in a static RAM is connected to a bit line through an accessing MOSFET. The accessing MOSFET has its gate connected to a word line. A word line driver comprising a level shifting N channel MOSFET and a CMOS inverter is connected to the word line. At the time of selecting the word line, a potential which is lower, by a threshold voltage of the MOSFET, than a power-supply potential is applied to the word line. Thus, a sub-threshold current flowing in the MOSFET connected between the storage node for storing data at a high level and the bit line to which data of a high level is read out becomes substantially small, so that a potential of the storage node for storing data of a high level is not lowered.Other References
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