In-system programmable logic device
Patent 4879688 Issued on November 7, 1989. Estimated Expiration Date: 
November 7, 2006. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
November 7, 2006. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesIntegrated programmable logic arrangement Non-volatile, electrically erasable and reprogrammable memory element Apparatus for signature and/or direct analysis of digital signals used in testing digital electronic circuits User reprogrammable programmed logic array Programmable logic array device using EPROM technology Programmable array logic circuit with testing and verification circuitry Programmable logic device Patent #: 4761768 InventorsAssigneeApplicationNo. 862815 filed on 05/13/1986US Classes:365/185.22, Verify signal326/38, Having details of setting or programming of interconnections or logic functions326/39, Array (e.g., PLA, PAL, PLD, etc.)326/88, With capacitive or inductive bootstrapping365/185.17, Logic connection (e.g., NAND string)365/185.23, Drive circuitry (e.g., word line driver)365/189.08, Including specified plural element logic arrangement708/230, Multifunctional714/725Programmable logic array (PLA) testingExaminersPrimary: Popek, Joseph A.Attorney, Agent or FirmInternational ClassesH03K 019/77G06F 011/26 AbstractAn in-system programmable logic device is disclosed which may be configured or reconfigured while installed in a user's system. The disclosed device employs non-volatile memory cells such as floating gate transistors as the programmable elements, and hence the device retains a particular programmed logic configuration virtually indefinitely during a powered-down state. The device is operable in a normal state and in several utility states for reconfiguring the device. The device state is controlled by an internal state machine which executes several state equations whose variables are the logic levels driving two dedicated pins and the present device state. One device pin receives serial input data which loads a shift register latch. The contents of the latch are employed to select a particular row of the cells to be programmed and the logic level to which the selected cells are to be programmed. The device normal inputs and outputs are isolated from the device during the utility states, so that the user's system does not affect the device operation during the utility states. A voltage multiplier circuit is included to generate the high voltage level necessary to program the floating gate transistors employed as the device memory cells from the device supply voltage, thereby further conserving on the required number of device pins. By programming a particular memory cell, the user may select the state of the device outputs during the utility states as either a present data latched condition or a tri-stated condition.Other References
Field of SearchTesting | |
