Method to produce via holes in polymer dielectrics for multiple electronic circuit chip packaging
Excimer laser patterning of a novel resist
Multichip integrated circuit packaging configuration and method Patent #: 4783695
ApplicationNo. 283095 filed on 12/12/1988
US Classes:216/21, Repairing circuit156/247, With stripping of adhered lamina156/344, Delaminating, per se216/83, NONGASEOUS PHASE ETCHING OF SUBSTRATE216/90, Relative movement between the substrate and a confined pool of etchant216/106, Etchant contains acid216/108, Etchant contains acid257/E21.512, Right-up bonding (EPO)257/E23.178Chips being integrally enclosed by interconnect and support structures (EPO)
ExaminersPrimary: Powell, William A.
Attorney, Agent or Firm
International ClassesC23F 001/02
AbstractA simplified method of gaining access to, for the purpose of replacing, a defective integrated circuit chip situated in a high density interconnect (HDI) circuit (10) comprises heating the HDI circuit to a temperature at which the peel strength of an adhesive (16) bonding a polymer overlay layer (18) to the tops of integrated circuit chips (4, 6, and 8) positioned on a substrate (12) is reduced. The polymer overlay layer, which may comprise one or multiple layers, is then peeled from the chips. The adhesive is present in sufficient quantity to protect the chips. The adhesive is then dissolved by subjecting the substrate to different solvents of successively lower solubility for the adhesive. Metal divots (34) left on chip pads (36) are removed by selectively etching copper in the presence of ultrasonic agitation. The entire circuit is finally subjected to a high pressure spray to remove any particulate remaining on the chips, so that the defective chip may be readily replaced without damaging or contaminating the HDI circuit.