Programmable logic array having a changeable logic structure

Patent 4876466 Issued on October 24, 1989. Estimated Expiration Date:

November 10, 2008. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Inventors

Application

No. 269763 filed on 11/10/1988

US Classes:

326/38, Having details of setting or programming of interconnections or logic functions257/E27.102, Read-only memory, ROM, structure (EPO)326/45, Complementary FET`s708/232Array of elements (e.g., AND/OR array, etc.)

Examiners

Primary: Miller, Stanley D.
Assistant: Wambach, M. R.

Attorney, Agent or Firm

Lowe, Price, LeBlanc, Becker & Shur

International Classes

G06F 007/38
H03K 019/094

Foreign Application Priority Data

1987-11-20 JP

Abstract

Programmable Logic Array PLA) cells are arranged at intersections of input lines and output lines of the array. Particular PLA cells to be programmed are arbitrarily selected by word line and bit line decoders. Switches for programming the PLA cells to implement a desired logic function are controlled by data stored in a random access memory whereby programming of the PLA can be changed arbitrarily and during operation of a system including the PLA.

Other References

Neil H. E. Weste et al., "Principles of CMOS VLSI Design" (Addison-Wesley Publishing 1985) pp. 368-379
Amar Mukherjee, "Introduction to nMOS and CMOS VLSI Systems Design" pp. 5206