Method of making asymmetrically optimized CMOS field effect transistors
May 1, 2009. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3686080 3747200 3887993 Process for patterning metal connections on a semiconductor structure by using a tungsten-titanium etch resistant layer Method of making MOS device by forming self-aligned polysilicon and tungsten composite gate Oxide trench structure for polysilicon gates and interconnects Self-aligned manufacture of FET Use of selectively deposited tungsten for contact formation and shunting metallization Process for forming LDD MOS/CMOS structures Self-aligned transistor method InventorAssigneeApplicationNo. 345875 filed on 05/01/1989US Classes:438/231, Plural doping steps257/369, Complementary insulated gate field effect transistors257/408, Including lightly doped drain portion adjacent channel (e.g., lightly doped drain, LDD device)257/E21.435, Lateral single gate single channel silicon transistor with both lightly doped source and drain extensions and source and drain self-aligned to sides of gate, e.g., LDD MOSFET, DDD MOSFET (EPO)257/E21.634, With particular manufacturing method of source or drain, e.g., specific S or D implants or silicided S or D structures or raised S or D structures (EPO)438/233, And contact formation438/586Combined with formation of ohmic contact to semiconductor regionExaminersPrimary: Hearn, Brian E.Assistant: Thomas, T. Attorney, Agent or FirmInternational ClassH01L 021/265AbstractA process for forming an asymmetrically structured pair of CMOS field effect transistors having feature refinements matched to the individual idiosyncrasies of the p-channel and n-channel transistors. Complementary transistors are formed using a single photolithographic mask and a fabrication sequence which begins with the p-channel transistor source/drain formation. Thereafter, the p-channel transistor source/drain regions are metalized, the n-channel transistor lightly doped drain regions are formed, and the sidewall dielectric spaced n-channel transistor source/drain regions are formed using the p-channel metalization as a mask. The p-channel transistor source/drain metalization suppresses the effects of the relatively greater p-type source/drain resistivity, while the LDD structure of the n-channel transistor reduces performance degradation attributable to hot electron trapping. The structural asymmetry attributable to the process materially offsets performance limitations common to the individual CMOS transistor types. | |
