U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Multicomputer digital processing system

Patent 4870704 Issued on September 26, 1989. Estimated Expiration Date: Icon_subject September 26, 2006. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Process for controlling operation of and data exchange between a plurality of individual computers with a control computer
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Multiprocessor system
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Selection of addressed processor in a multi-processor network
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Computer system with two busses
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Inventor: Lapp, Jr.

Multiprocessor system
Patent #: 4404628
Issued on: 09/13/1983
Inventor: Angelo

Multi-processor data communication bus structure
Patent #: 4417303
Issued on: 11/22/1983
Inventor: Korowitz ,   et al.

Data processing system having multiple buses
Patent #: 4456965
Issued on: 06/26/1984
Inventor: Graber ,   et al.

Device wherein a central sub-system of a data processing system is divided into several independent sub-units
Patent #: 4472771
Issued on: 09/18/1984
Inventor: Bienvenu ,   et al.

Modular computer system
Patent #: 4484273
Issued on: 11/20/1984
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Dual path bus structure for computer interconnection
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Issued on: 12/25/1984
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Inventors

Assignee

Application

No. 06/666991 filed on 10/31/1984

US Classes:

710/120Hierarchical or multilevel accessing

Examiners

Primary: Shaw, Gareth D.
Assistant: Fairbanks, Jonathan C.

Attorney, Agent or Firm

International Classes

G06F 9/46 (20060101)
G06F 13/40 (20060101)
G06F 13/36 (20060101)
G06F 1/10 (20060101)
H05K 7/14 (20060101)
H01R 12/16 (20060101)
H01R 12/00 (20060101)
G06F 11/20 (20060101)
G06F 11/22 (20060101)
G06F 11/34 (20060101)
G06F 11/273 (20060101)

Abstract

A multiple computer digital processing system including several Local Buses positioned orthogonally to a Common Bus. Each Local Bus is connected to the Common Bus through a plugably connected Common Bus interface card to provide a transfer of information between Local Buses across the Common Bus. Computer cards, memory cards and other device cards may be plugably connected to the Local Bus to communicate with each other via the Local Buses and Common Bus. The number and types of cards connected and even the number of Local Buses connected to the Common Bus may be varied according to the requirements of each application. Additionally, the Common Bus includes a shared memory accessible by all devices and an InterComputer Interrupt circuit providing interrupts to the computer cards. Further the computer cards are plugably connectable to a Peripheral Bus to provide communications with peripheral devices located externally to the system. All cards connected to the Local Buses and Common Bus include monitor circuits connected through a Test Bus to a System Monitor that configures the system according to the cards connected and the application requirements, detects errors, monitors performance, and provides fault tolerant repair capability under operator supervision.

Other References

  • "VME Bus Specification Manual", Revision A, Oct. 1981, Motorola
  • IBM Synchronous Data Link Control General Information, Third Edition, 1979, IBM Corporation
  • Katsuki et al., "Pluribus-An Operational Fault-Tolerant Multiprocessor," Proceedings of the IEEE, vol. 66, No. 10, Oct. 1978, pp. 1146-1159
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