Patent ReferencesProcess for controlling operation of and data exchange between a plurality of individual computers with a control computer Multiprocessor system Selection of addressed processor in a multi-processor network Computer system with two busses Multiprocessor system Multi-processor data communication bus structure Data processing system having multiple buses Device wherein a central sub-system of a data processing system is divided into several independent sub-units Modular computer system Dual path bus structure for computer interconnection Inventors
AssigneeApplicationNo. 06/666991 filed on 10/31/1984US Classes:710/120Hierarchical or multilevel accessingExaminersPrimary: Shaw, Gareth D.Assistant: Fairbanks, Jonathan C. Attorney, Agent or FirmInternational ClassesG06F 9/46 (20060101)G06F 13/40 (20060101) G06F 13/36 (20060101) G06F 1/10 (20060101) H05K 7/14 (20060101) H01R 12/16 (20060101) H01R 12/00 (20060101) G06F 11/20 (20060101) G06F 11/22 (20060101) G06F 11/34 (20060101) G06F 11/273 (20060101) AbstractA multiple computer digital processing system including several Local Buses positioned orthogonally to a Common Bus. Each Local Bus is connected to the Common Bus through a plugably connected Common Bus interface card to provide a transfer of information between Local Buses across the Common Bus. Computer cards, memory cards and other device cards may be plugably connected to the Local Bus to communicate with each other via the Local Buses and Common Bus. The number and types of cards connected and even the number of Local Buses connected to the Common Bus may be varied according to the requirements of each application. Additionally, the Common Bus includes a shared memory accessible by all devices and an InterComputer Interrupt circuit providing interrupts to the computer cards. Further the computer cards are plugably connectable to a Peripheral Bus to provide communications with peripheral devices located externally to the system. All cards connected to the Local Buses and Common Bus include monitor circuits connected through a Test Bus to a System Monitor that configures the system according to the cards connected and the application requirements, detects errors, monitors performance, and provides fault tolerant repair capability under operator supervision.Other References
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