FSK demodulation circuit
Patent 4870659 Issued on September 26, 1989. Estimated Expiration Date: 
August 29, 2008. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
August 29, 2008. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesFrequency shift offset quadrature modulation and demodulation Offset QPSK demodulator and receiver Zero-IF receiver wih feedback loop for suppressing interfering signals Procedure and circuit for detection of the information of a received signal Frequency demodulator for recovering digital signals Patent #: 4752742 InventorsApplicationNo. 07/237535 filed on 08/29/1988US Classes:375/328, Including switching or gating (digital circuits)329/303, Including logic element (e.g., logic gate or flip-flop375/334, Frequency shift keying375/340Particular pulse demodulator or detectorExaminersPrimary: Safourek, Benedict V.Assistant: Chin, Stephen Attorney, Agent or FirmInternational ClassesH04L 27/144 (20060101)H04L 27/152 (20060101) Foreign Application Priority Data1987-08-29 JPAbstractAn FSK demodulation circuit which receives as input an FSK modulated reception signal, obtains two quadrature pulse trains, i.e., a first pulse train and a second pulse train, from a phase detection circuit, is provided with at least two sampling means which use the edge of one of the pulse trains and sample the logic of the other pulse train, produces two or more sample outputs at different timings, and determines the logic of the reproduced data from a combination of the logics "1" and "0" of the sample outputs.Other References
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