Method of making insulated-gate field effect transistor
December 29, 2008. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesDouble polycrystalline silicon gate memory device Process for producing a semiconductor device Fabrication of submicron semiconductor devices Fabrication of FETs Self-aligned metal field effect transistor integrated circuits using polycrystalline silicon gate electrodes Method for manufacturing semiconductor device Method of forming self-aligned contact openings GaAs short channel lightly doped drain MESFET structure and fabrication Process for fabricating semiconductor integrated circuit device Method of manufacturing an insulated gate field effect device InventorAssigneeApplicationNo. 07/291571 filed on 12/29/1988US Classes:438/297, Recessed oxide formed by localized oxidation (i.e., LOCOS)257/E21.166, Conductive layer comprising semiconducting material (EPO)257/E21.305, Physical or chemical etching of layer, e.g., to produce a patterned layer from pre-deposited extensive layer (EPO)257/E21.433, Where the source and drain or source and drain extensions are self-aligned to sides of gate (EPO)438/301, Source or drain doping438/586, Combined with formation of ohmic contact to semiconductor region438/672Plug formation (i.e., in viahole)ExaminersPrimary: Hearn, Brian E.Assistant: Everhart, B. Attorney, Agent or FirmInternational ClassesH01L 21/02 (20060101)H01L 21/285 (20060101) H01L 21/336 (20060101) H01L 21/3213 (20060101) Foreign Application Priority Data1987-12-29 JPAbstractA method of manufacturing an insulated-gate field effect transistor is comprised of forming on a semiconductor substrate a gate electrode elecrically insulated from the substrate. A flat insulating film of silicon oxide is formed over the substrate. A pair of openings are formed through the flat insulating film at both sides of the gate electrode such that opposite side thereof are etched and exposed. An oxide film is formed on the exposed side edges of the gate electrode. Impurities are implanted through the pair of openings into the substrate to form source and drain regions. An electroconductive polysilicon film is deposited over the substrate. The deposited polysilicon film is polished to leave a part thereof selectively in the openings to thereby form electrical contacts to the source and drain regions through the openings.Other References
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