U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Communications circuit having an interface for external address decoding

Patent 4866421 Issued on September 12, 1989. Estimated Expiration Date: Icon_subject June 18, 2007. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Microprocessor device with integrated auto-loaded timer
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Inventor: Kempf

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Patent #: 4638477
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Inventor: Okada ,   et al.

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Patent #: 4674086
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Inventor: Szczepanek ,   et al.

Method and apparatus for bridging local area networks
Patent #: 4706081
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Patent #: 4715030
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Inventor

Assignee

Application

No. 07/064289 filed on 06/18/1987

US Classes:

340/825.52, Addressing370/452On ring or loop

Examiners

Primary: Yusko, Donald J.
Assistant: Holloway, III, Edwin C.

Attorney, Agent or Firm

International Class

H04L 12/46 (20060101)

Abstract

An adapter circuit for a local area network is disclosed, which contains logic external to the protocol handler for address comparison. The adapter uses random-access memory to store the data fields arriving after the address fields in the serial input data stream during such time as the adapter is comparing the address fields to its own address. The portion of memory used for the data storage is overwritten (recovered) by the next frame of data if the particular adapter was not addressed by the prior frame; the portion of memory used for the data storage is not overwritten if the data was addressed to the adaptor. The protocol handler circuit performs an address comparison internally thereto, for intra-ring communication, and controls the recovery of the memory dependent upon the results of the comparison. The external logic performs an address comparison, primarily in inter-ring communication. An interface is provided within the protocol handler circuit to disable the recovery of the memory in the event of a true comparison found by the external logic, regardless of the results of the comparison performed by the protocol handler circuit itself. Two bi-directional signal lines are used for communication betwen the protocol handler circuit and the external logic. The protocol handler circuit sets a logic state on both lines to indicate the beginning of a frame, and one line or the other is set by the external logic to communicate its results.

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