Multiplexed bus architecture for configuration sensing
July 18, 2008. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesBus line drive circuit Interface circuit for interconnecting peripherals to an information processing device Biasing network for multifunction bipolar integrated system Chip-on-chip semiconductor device having selectable terminal connections Control circuit with plural individual selectable controls Electronic EC for minimizing EC pads Semiconductor device Patent #: 4808844 InventorsAssigneeApplicationNo. 07/220533 filed on 07/18/1988US Classes:326/57, With field effect-transistor326/86, Bus driving327/408, Field-effect transistor340/14.3, Programmable708/230MultifunctionalExaminersPrimary: Miller, Stanley D.Assistant: Bertelson, David R. Attorney, Agent or FirmInternational ClassesG06F 15/16 (20060101)G06F 13/40 (20060101) G06F 15/177 (20060101) AbstractThe invention provides a circuit for use with a standard bidirectional databus having an active current device providing a first logic level in combination with a selectably jumpered passive resistance device providing a second logic level, the active element responsive to an enable signal whereby tristating the bus write drivers and reading the bus will sense a configuration determined by selection of the jumper. | |
