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US Patent 4864629 - Image correlation system
US Patent Issued on September 5, 1989
Estimated Patent Expiration Date:
December 17, 2007Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
Estimated Patent Expiration Date:
December 17, 2007Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.AbstractA method and apparatus for controlling a parallel combination of correlation circuits which compare image pixels. A number of correlation circuits are provided, each having its own memory. The memories are loaded with image data with each memory being assigned a different block (region) of the image. Each memory is also loaded with an overlapping portion of an adjacent block so that a pattern can be stepped across the entire block, including a match of the first column of the pattern with the last column of the block. The loading is done by generating addresses corresponding to addresses for the source image with one or more of the most significant bits modified so that the address sequence received by the second and subsequent memories are identical to the address sequence received by the first memory. This allows the various blocks of the image in the different memories to be later simulataneously accessed in parallel using a single address sequence. | InventorApplicationNo. 07/134590 filed on 12/17/1987US Classes:382/216, At multiple image orientations or positions365/239, Sequential382/218, Comparator382/278, Correlation708/424Multidimensional dataExaminersPrimary: Boudreau, Leo H.Attorney, Agent or FirmUS Patent References4429414, Pattern recognition system operating by the multiple similarity methodIssued on: 01/31/1984 Inventor: Asakawa4434502, Memory system handling a plurality of bits as a unit to be processed Issued on: 02/28/1984 Inventor: Arakawa , et al.4484349, Parallel pipeline image processor Issued on: 11/20/1984 Inventor: McCubbrey4498141, High speed correlation circuit and method Issued on: 02/05/1985 Inventor: Cooper4543660, Pattern features extracting apparatus and method Issued on: 09/24/1985 Inventor: Maeda4561072, Memory system handling a plurality of bits as a unit to be processed Issued on: 12/24/1985 Inventor: Arakawa , et al.4566082, Memory pack addressing system Issued on: 01/21/1986 Inventor: Anderson4644503Computer memory system with integrated parallel shift circuits Issued on: 02/17/1987 Inventor: Bantz , et al. International ClassesG06K 9/64 (20060101)G06F 17/15 (20060101) |
