Semiconductor read/write memory array having serial access
Programmable logic device Patent #: 4761768
ApplicationNo. 07/262493 filed on 10/25/1988
US Classes:326/38, Having details of setting or programming of interconnections or logic functions326/39, Array (e.g., PLA, PAL, PLD, etc.)326/88, With capacitive or inductive bootstrapping365/185.01, FLOATING GATE365/185.17, Logic connection (e.g., NAND string)365/189.08, Including specified plural element logic arrangement365/200, Bad bit365/233, Sync/clocking708/230Multifunctional
ExaminersPrimary: Popek, Joseph A.
Attorney, Agent or Firm
International ClassesH03K 19/177 (20060101)
G01R 31/28 (20060101)
G01R 31/3185 (20060101)
AbstractAn in-system programmable logic device is disclosed which may be configured or reconfigured while installed in a user's system. The disclosed device employs non-volatile memory cells such as floating gate transistors as the programmable elements, and hence the device retain a particular programmed logic configuration virtually indefinitely during a powered-down state. The device is operable in a normal state and in several utility states for reconfiguring the device. The device state is controlled by an internal state machine which executes several state equations whose variables are the logic levels driving two dedicated pins and the present device state. One device pin receives serial input data which loads a shift register latch. The contents of the latch are employed to select a particular row of the cells to be programmed and the logic level to which the selected cells are to be programmed. The device normal inputs and outputs are isolated from the device during the utility states, so that the user's system does not affect the device operation during the utility states. A voltage multiplier circuit is included to generate the high voltage level necessary to program the floating gate transistors employed as the device memory cells from the device supply voltage, thereby further conserving on the required number of device pins. By programming a particular memory cell, the user may select the state of the device outputs during the utility states as either a present data latched condition or a tri-stated condition.