Abstract

An image enhancement apparatus for performing connection processing for connecting only omissions in an input line figure, including a background figure skeletonization circuit for skeletonizing background pixel data of binary image f0 obtained by digitizing a line figure into one-line pixel data and the background pixel data, skeletonization being performed to the degree of a one-dot line width, and for generating image f1, a gap filling cirucit for generating image f2 obtained by pixel data of the one-dot line width of image f1 into on-line pixel data, a connection pixel detector for skeletonizing the on-line pixel data of image f2 by a predetermined number of steps and generating image f3, a connection candidate detector for calculating adjacent pixels of the on-line pixel of image f0 according to an AND signal of image f0 and its inverted image f0 and for generating image f4 representing a connection candidate area, a connection pixel thickening circuit for thickening the one-dot line width pixel data of image f3 within image f4 and for generating image f5, and an OR circuit for generating an OR signal of images f0 and f5.

Other References

• Image Analysis and Mathematical Morphology; J. Serra; 1982, Academic Press, pp. 40-41
• A Reader for Logic Circuit Diagrams; T. Kondo, M. Tabata, M. Kidode; 1983, Proceeding of 27th IPSJ, pp. 961-962
• Tosgraph, A Reader for Hand-Written Diagrams; H. Kurasaki, K. Mori, S. Tsunekawa; 1985, Proceeding of 30th IPSJ, pp. 1211-1212