Programmable variable-cycle clock circuit for skew-tolerant array processor architecture
June 19, 2007. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesApparatus for dead track recovery Peripheral device controller for a data processing system Phase-locked loop clock pulse extraction circuit Clock derivation circuit for double frequency encoded serial digital data Synchronizing signal detection protective circuit Sampled towed array telemetry Circuit for extending a multiplexed address and data bus to distant peripheral devices Data processor system clock checking system Systolic array apparatuses for matrix computations Associative processor with variable length fast multiply capability InventorsApplicationNo. 07/064970 filed on 06/19/1987US Classes:713/500, CLOCK, PULSE, OR TIMING SIGNAL GENERATION OR ANALYSIS712/15ReconfiguringExaminersPrimary: Williams, Archie E. Jr.Assistant: Harrell, Robert B. Attorney, Agent or FirmInternational ClassesG06F 1/08 (20060101)G06F 1/04 (20060101) G06F 15/76 (20060101) G06F 1/10 (20060101) G06F 15/80 (20060101) AbstractUsing a variable-duration clock circuit, together with programmable duration control to alter the clock waveform within strict rules, permits the programmer to arrange appropriately short durations for short data transfers, and to arrange appropriately longer durations for longer data transfers in an array processor of myriad processing elements. There is no need to allow sufficient time in every clock cycle for worst case data transfer between remote processing elements.The clock waveform has three recognizable edges (A,B,C) regardless of loss of sharpness during its travel to the various processing elements. The convention that three skew-sensitive activities, READ, WRITE and OPERAND SUPPLY conform to respectively assigned edges as follows:A=READ;B=OPERAND SUPPLY;C=WRITE (Read next)The processing elements synchronize with the clock waveform, which is optimized for the instructions of the program being executed. There is no time wasted allowing for worst case data transfers possible in certain instructions but not possible in other instructions.Other References
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