Reducing power consumption in calculators
Circuit for reducing power consumption in battery operated microprocessor based systems
Power supply circuit for a data processor
Power consumption control system for electronic digital data processing devices
Low power consumption data processing system
Clocked logic low power standby mode
Turn-off-processor between keystrokes
Power saving device for an electronic musical instrument
Data processing apparatus capable of transferring serial data with small power consumption
ApplicationNo. 06/820460 filed on 01/17/1986
US Classes:713/601, Inhibiting timing generator or component365/227, Conservation of power713/321, Programmable calculator with power saving feature713/322By clock speed control (e.g., clock on/off)
ExaminersPrimary: Williams, Archie E. Jr.
Assistant: Coleman, Eric
Attorney, Agent or Firm
International ClassG06F 1/32 (20060101)
AbstractAn apparatus and method are provided for disabling the clocking of a processor in a battery operated computer during non-processing times. The clocking is disabled at the conclusion of a processing operation. The clocking can then be re-enabled using interrupts from any one of a plurality of sources, such as an I/O device or a direct memory access. Application programs and operating system programs running on the system can specify the stopping of the system clock and the central processor until a specified event which had been requested occurs, or until an optional time-out period has expired. In this situation, the event is defined as one that results in either a system interrupt from an I/O device or from a direct memory access operation. The stopping of the system clock is a two part operation wherein in the first part the stopping mechanism is first armed. If an interrupt is received subsequent to arming, then it will be processed and the arming mechanism will be reset. However, if an interrupt does not occur after arming within a specified time period, then the system clock will be stopped.