Dynamic logic circuit including bipolar transistors and field-effect transistors

Patent 4849658 Issued on July 18, 1989. Estimated Expiration Date:

August 4, 2007. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

Dynamic CMOS logic circuits for implementing multiple AND-functions
Patent #: 4569032
Issued on: 02/04/1986
Inventor: Lee

FET-bipolar switching device and circuit
Patent #: 4604535
Issued on: 08/05/1986
Inventor: Sasayama , et al.

Bi-MOS buffer circuit
Patent #: 4694202
Issued on: 09/15/1987
Inventor: Iwamura , et al.

Consistent precharge circuit for cascode voltage switch logic Patent #: 4700086
Issued on: 10/13/1987
Inventor: Ling , et al.

Inventors

Assignee

Hitachi, Ltd.

Application

No. 07/081696 filed on 08/04/1987

US Classes:

326/110, Bi-CMOS326/30, Bus or line termination (e.g., clamping, impedance matching, etc.)326/98MOSFET

Examiners

Primary: Hudspeth, David

Attorney, Agent or Firm

Antonelli, Terry & Wands

International Classes

G06F 7/48 (20060101)
G06F 7/50 (20060101)
G11C 7/00 (20060101)
H03K 19/177 (20060101)
H03K 19/096 (20060101)
G11C 7/12 (20060101)

Foreign Application Priority Data

1986-08-08 JP

Abstract

A dynamic logic circuit is provided which is arranged to realize high speed operation. At least one bipolar transistor is provided having a collector, a base and an emitter, with the collector-emitter current path connected between the output of the dynamic logic circuit and a first potential. A precharging device is coupled between a second potential and the output of the dynamic logic circuit to precharge the output according to at least one clock signal which periodically changes its state. Further, at least two field-effect transistors are provided, wherein one assumes an on or off state opposite to that of the precharging means in response to the clock signal while the other operates in response to at least one input signal. The two field-effect transistors have their source-drain current paths connected between the output of the dynamic logic circuit and the base of the bipolar transistor.