Method for making folded extended window field effect transistor
Patent 4844776 Issued on July 4, 1989. Estimated Expiration Date: 
December 4, 2007. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
December 4, 2007. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod of fabricating MOS field effect transistors Fabrication of FETs Patent #: 4453306 InventorsApplicationNo. 07/128834 filed on 12/04/1987US Classes:438/303, Utilizing gate sidewall structure257/E21.59, Local interconnects; local pads (EPO)438/305, Plural doping steps438/586Combined with formation of ohmic contact to semiconductor regionExaminersPrimary: Powell, William A.Attorney, Agent or FirmInternational ClassesH01L 21/768 (20060101)H01L 21/70 (20060101) H01L 21/336 (20060101) H01L 21/02 (20060101) AbstractA gate electrode having an insulating top layer as well as insulating sidewall spacers permits the source and drain regions to be electrically contacted through windows directly above the source and drain regions formed in a window pad layer. The window pad layer may also be used as a sublevel interconnect.Other References
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