Automatic logic design system
December 24, 2006. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesAutomated design program for LSI and VLSI circuits Method for manufacturing a gate array integrated circuit device Method for manufacturing a custom-circuit LSI, and a gate array device Hierarchical, computerized design of integrated circuits Method and structure for use in designing and building electronic systems in integrated circuits Routing method in computer-aided-customization of universal arrays and resulting integrated circuit Computer aided design method and apparatus comprising means for automatically generating pin-to-pin interconnection lists between respective discrete electrical component circuits Method and system of circuit pattern understanding and layout Routing method for use in wiring design Patent #: 4752887 InventorsAssigneeApplicationNo. 06/945946 filed on 12/24/1986US Classes:716/11, Layout editor (e.g., updating)716/2, Optimization (e.g., redundancy, compaction)716/3Translation (e.g., conversion, equivalence)ExaminersPrimary: Shaw, Gareth D.Assistant: Kriess, Kevin A. Attorney, Agent or FirmInternational ClassG06F 17/50 (20060101)Foreign Application Priority Data1986-01-08 JPAbstractHerein disclosed is an automatic design system for automatically generating a data structure, which is only implicitly expressed by a logic specification description, by deriving, in case a logic system has data structures of similar constructions, one data structure from the structure description and transfer behavior description of the other data structure. | |
