Method for fabricating semiconductor device and etchant for polymer resin
Method of improving the adherence of metallic conductive lines on polyimide layers
Method of making conductive paths through a lamina in a semiconductor device
Polymeric insulation layer etching process and composition
Process for etching tapered polyimide vias Patent #: 4560436
ApplicationNo. 07/115722 filed on 11/02/1987
US Classes:257/759, Including organic insulating material between metal levels216/13, FORMING OR TREATING ELECTRICAL CONDUCTOR ARTICLE (E.G., CIRCUIT, ETC.)216/48, Mask is exposed to nonimaging radiation257/774, Via (interconnection hole) shape257/E21.502, Encapsulation, e.g., encapsulation layer, coating (EPO)257/E21.587, By deposition over sacrificial masking layer, e.g., lift-off (EPO)430/313, With formation of resist image, and etching of substrate or material deposition430/317, Insulative or nonmetallic dielectric etched438/612, Forming solder contact or bonding pad438/670, Utilizing lift-off438/951Lift-off
ExaminersPrimary: Powell, William A.
Attorney, Agent or Firm
International ClassesH01L 21/768 (20060101)
H01L 21/70 (20060101)
H01L 21/56 (20060101)
H01L 21/02 (20060101)
AbstractThis process uses a metal lift-off step and results in a layer of polyimide covering the surface of an integrated circuit, except at the bonding pads which are covered by metals. A layer of polyimide is applied to the surface of an integrated circuit and then partially cured. A layer of positive photo-resist is applied over the polyimide layer and then pattern exposed and developed, resulting in windows being opened up over the bonding pads of the integrated circuit. The remaining photo-resist is then flood exposed. One or more metals are then sputtered over the resist and the bonding pads. The integrated circuit is then immersed in solvent and the remaining layer of photo-resist, including the metal above it, is lifted-off. Only the metal over the bonding pads remains. The polyimide layer is then fully cured.