Mixed-precision floating point operations from a single instruction opcode
November 12, 2007. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesData processing system for multi-precision arithmetic Arithmetic logic unit for floating point data and/or fixed point data Information processing system Multi-precision fixed/floating-point processor Method and apparatus for floating point operations Floating-point data rounding and normalizing circuit Condition code producing system Patent #: 4788655 InventorsApplicationNo. 07/119547 filed on 11/12/1987US Classes:712/222, Floating point or vector708/551Round off or truncationExaminersPrimary: Harkcom, Gary V.Assistant: Lynt, Christopher H. Attorney, Agent or FirmInternational ClassesG06F 7/48 (20060101)G06F 7/57 (20060101) AbstractApparatus for performing mixed precision calculations in the floating point unit of a microprocessor from a single instruction opcode. 80-bit floating-point registers (44) may be specified as the source or destination address of a floating-point instruction. When the address range of the destination indicates (26) that a floating point register is addressed, the result of that operation is not rounded to the precision specified by the instruction, but is rounded (58) to extended 80-bit precision and loaded into the floating point register (FP-44). When the address range of the source indicates (26) that an FP register is addressed, the data is loaded from the FP register in extended precision, regardless of the precision specified by the instruction. In this way, real and long-real operations can be made to use extended precision numbers without explicitly specifying that in the opcode. | |
