Fabrication of FETs with source and drain contacts aligned with the gate electrode

Patent 4822754 Issued on April 18, 1989. Estimated Expiration Date:

April 18, 2006. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

Method of making self-aligned device
Patent #: 4319395
Issued on: 03/16/1982
Inventor: Lund , et al.

Method of making contact electrodes to silicon gate, and source and drain regions, of a semiconductor device
Patent #: 4343082
Issued on: 08/10/1982
Inventor: Lepselter , et al.

Fabrication of FETs Patent #: 4453306
Issued on: 06/12/1984
Inventor: Lynch , et al.

Inventors

Application

No. 06/619892 filed on 06/12/1984

US Classes:

438/586, Combined with formation of ohmic contact to semiconductor region257/E21.166, Conductive layer comprising semiconducting material (EPO)257/E21.433, Where the source and drain or source and drain extensions are self-aligned to sides of gate (EPO)257/E29.122, Characterized by relative position of source or drain electrode and gate electrode (EPO)257/E29.146, On silicon (EPO)438/592, Possessing plural conductive layers (e.g., polycide)438/684, Electrically conductive polysilicon438/694, Combined with coating step438/705Altering etchability of substrate region by compositional or crystalline modification

Examiners

Primary: Hearn, Brian E.
Assistant: Quach, T. N.

Attorney, Agent or Firm

Birnbaum; Lester H.

International Classes

H01L 21/336 (20060101)
H01L 21/285 (20060101)
H01L 29/417 (20060101)
H01L 21/02 (20060101)
H01L 29/45 (20060101)
H01L 29/40 (20060101)

Abstract

A method of fabricating FETs to reduce parasitics. Contact is made to the source and drain regions through a polycrystalline silicon runner which is aligned with the edge of the gate electrode. This is accomplished by providing a multi-level electrode structure including a gate electrode and depositing the polycrystalline silicon layer over the device. The polycrystalline silicon is rendered selectively removable in the portion overlying the gate electrode. When this portion is removed, the remaining polycrystalline is aligned with the gate.

Other References

Proposed for publication in IEEE Electron Device Letters: "A New MOSFET Structure with Self-Aligned Polysilicon Source and Drain Electrodes," by D. S. Oh and C. Kim