Digital phase lock loop
Automatic clock positioning circuit for a digital data transmission system
Digital timing recovery system
Digital phase lock loop for flexible disk data recovery system
Clock recovery apparatus for phase shift keyed encoded data
Digital PLL decoder Patent #: 4584695
ApplicationNo. 07/123040 filed on 11/19/1987
US Classes:375/376, Phase locked loop375/371Phase displacement, slip or jitter correction
ExaminersPrimary: Pellinen, A. D.
Assistant: Jennings, Derek S.
Attorney, Agent or Firm
International ClassesH03L 7/08 (20060101)
H03L 7/091 (20060101)
H04L 7/033 (20060101)
H03L 7/081 (20060101)
H04L 7/00 (20060101)
AbstractA digital clock recovery scheme is disclosed. A reference clock, is used to provide a plurality of N signals with different clock phases. The incoming data stream is sampled and clocked with the reference clock to generate a plurality of M samples for each data bit. The logic values of the M samples are then analyzed to determine the relationship between the current clock phase and the data bit transition. In particular, if all samples agree, the clock phase is correctly aligned with the data. If the clock phase is either leading or lagging the data, various samples will disagree. In the latter situation, the clock phase is adjusted until all samples agree, the particular clock which provides this state thus being defined as the recovered clock signal.