U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Memory back up system with one cache memory and two physically separated main memories

Patent 4819154 Issued on April 4, 1989. Estimated Expiration Date: Icon_subject December 4, 2006. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

3588829

3736566

3761881

3889237

Apparatus for selectively clearing a cache store in a processor having segmentation and paging
Patent #: 3979726
Issued on: 09/07/1976
Inventor: Lange ,   et al.

Memory hierarchy system with journaling and copy back
Patent #: 4020466
Issued on: 04/26/1977
Inventor: Cordi ,   et al.

Instruction retry mechanism for a data processing system
Patent #: 4044337
Issued on: 08/23/1977
Inventor: Hicks ,   et al.

Multiprocessor system
Patent #: 4228496
Issued on: 10/14/1980
Inventor: Katzman ,   et al.

Protective colloid-free plastics dispersion having a bimodal particle size distribution
Patent #: 4395500
Issued on: 07/26/1983
Inventor: Lohr ,   et al.

Microprocessor which detects leading 1 bit of instruction to obtain microcode entry point address
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Issued on: 09/06/1983
Inventor: Sacarisen ,   et al.

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Inventors

Assignee

Application

No. 06/937978 filed on 12/04/1986

US Classes:

714/20Plural recovery data sets containing set interrelation data (e.g., time values or log record numbers)

Examiners

Primary: Zache, Raulfe B.
Assistant: Lee, Thomas C.

Attorney, Agent or Firm

International Classes

G06F 11/14 (20060101)
G06F 11/20 (20060101)
G06F 12/08 (20060101)
G11C 29/00 (20060101)

Abstract

Apparatus for maintaining duplicate copies of information stored in fault-tolerant computer main memories is disclosed. A non write-through cache memory associated with each of the system's processing elements stores computations generated by that processing element. At a context switch, the stored information is sequentially written to two separate main memory units. A separate status area in main memory is updated by the processing element both before and after each writing operation so that a fault occurring during data processing or during any storage operation leaves the system with sufficient information to be able to reconstruct the data without loss of integrity.To efficiently transfer information between the cache memory and the system main memories without consuming a large amount of processing time at context switches, a block status memory associated with the cache memory contains an entry for each data block in the cache memory. The entry indicates whether the corresponding data block has been modified during data processing or written with computational data from the processing element. The storage operations are carried out by high-speed hardware which stores only the modified data blocks. Additional special-purpose hardware simultaneously invalidates all cache memory entries so that a new task can be loaded and started.

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