Polycide process for integrated circuits
April 6, 2007. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesFabrication method for integrated circuits with polysilicon lines having low sheet resistance Composite conductive structures in integrated circuits Integrated semiconductor circuit structure and method for making it Conductivity WSi2 (tungsten silicide) films by Pt preanneal layering Doped polysilicon silicide semiconductor integrated circuit interconnections Silicon rich refractory silicides as gate metal Patent #: 4337476 InventorAssigneeApplicationNo. 07/034515 filed on 04/06/1987US Classes:438/592, Possessing plural conductive layers (e.g., polycide)257/E23.164, Containing semiconductor material, e.g., polysilicon (EPO)257/E29.146, On silicon (EPO)438/644, Having adhesion promoting layer438/654Having adhesion promoting layerExaminersPrimary: Hearn, Brian E.Assistant: Quach, T. N. Attorney, Agent or FirmInternational ClassesH01L 23/52 (20060101)H01L 29/45 (20060101) H01L 29/40 (20060101) H01L 23/532 (20060101) AbstractA process for making a semiconductor integrated circuit which has electrodes, contacts and interconnects composed of a multilayer structure including a layer of polycrystalline silicon with an overlying layer of a refractory metal silicide such as MoSi2 or WSi2. Adhesion of the metal silicide to the polysilicon is enhanced by forming a thin silicon oxide coating on the polysilicon before sputtering the metal silicide. The resulting structure has low resistance but retains the advantages of polysilicon on silicon.Other References
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