Low 1/f noise amplifier for CCD imagers

Patent 4814648 Issued on March 21, 1989. Estimated Expiration Date:

September 24, 2007. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

Balanced regenerative charge detection circuit for semiconductor charge transfer devices
Patent #: 4007381
Issued on: 02/08/1977
Inventor: Mohsen

Sensing circuit for semiconductor charge transfer devices
Patent #: 4075514
Issued on: 02/21/1978
Inventor: Sequin

Reduction of sparkle noise and mottling in CCD imagers
Patent #: 4223234
Issued on: 09/16/1980
Inventor: Levine

Low noise synchronous detection for a charge transfer device Patent #: 4644287
Issued on: 02/17/1987
Inventor: Levine

Inventor

Hynecek, Jaroslav

Assignee

Texas Instruments Incorporated

Application

No. 07/100668 filed on 09/24/1987

US Classes:

327/563, With differential amplifier327/212, With clock input330/253, Having field effect transistor377/63Charge-coupled device

Examiners

Primary: Miller, Stanley D.
Assistant: Callahan, Timothy P.

Attorney, Agent or Firm

International Classes

H03K 3/00 (20060101)
H03K 3/356 (20060101)
H04N 5/217 (20060101)

Abstract

A low 1/f noise amplifier has been provided for an output of a CCD imager. To reduce clock noise, the amplifier employs a differential detection scheme. Linear stages (54, 76) are coupled by capacitors (60, 82) to a differential amplifier (64). Differential amplifier (64) employs a first (112, 118) and a second (172, 198) differential transistor pair. The second differential pair (172, 198) is cross-coupled to the outputs of the first differential pair (112, 118) by load resistances (180, 206) with the voltage drop across them remaining substantially constant. To maintain stability, the positive and negative branches of the amplifier are periodically reset by a resetter (210). The input nodes (62, 86) are periodically reset to a voltage reference.