Power-on reset circuit
Patent 4812679 Issued on March 14, 1989. Estimated Expiration Date: 
November 9, 2007. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
November 9, 2007. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesPower-on reset pulse generator CMOS power-up reset circuit for gate arrays and standard cells Power-on reset circuit Voltage level sensing power-up reset circuit Patent #: 4717840 InventorAssigneeApplicationNo. 07/118074 filed on 11/09/1987US Classes:327/143Responsive to power supplyExaminersPrimary: Miller, Stanley D.Assistant: Bertelson, David R. Attorney, Agent or FirmInternational ClassH03K 17/22 (20060101)AbstractA power-on reset circuit includes a trigger voltage generating circuit which, when activated, causes current from a current source to be steered so as to charge a capacitor. When the voltage on the capacitor reaches a predetermined value, a switchable output stage is switched so as to generate the desired power-on reset signal. The trigger voltage generating circuit is responsive to a threshold voltage which tracks the power supply voltage and which is generated by separate circuitry. | |
