Flip-flop false output rejection circuit
Circuit for prevention of the metastable state in flip-flops
Retriggerable edge detector for edge-actuated internally clocked parts
Dual-clock edge triggered flip-flop circuits
Binary signal comparator using two d flip-flops for precise triggering
Dual-mode timer circuit
Edge programmable timing signal generator
Edge detector circuit and oscillator using same Patent #: 4710653
ApplicationNo. 07/123498 filed on 11/20/1987
US Classes:327/206, Including field-effect transistor327/198, Initializing, resetting, or protecting a steady state condition327/208Including field-effect transistor
ExaminersPrimary: Miller, Stanley D.
Assistant: Bertelson, David R.
Attorney, Agent or Firm
International ClassesH03K 3/00 (20060101)
H03K 3/356 (20060101)
AbstractAn edge-triggered latch is disclosed which has a low setup time and almost no metastability problem. It comprises a dynamic sensing means for detecting the voltage level of the data signal and at least one dynamic buffer for amplifying said detected voltage level into one of two logic levels recognizable by a static latch wherein the sampled result is stored.