Programmable interconnection chip for computer system functional modules
Patent 4807183 Issued on February 21, 1989. Estimated Expiration Date: 
June 23, 2008. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
June 23, 2008. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesData direction register for interface adaptor chip Status reporting with ancillary data Dynamic activity-creating data-driven computer architecture Memory-linked wavefront array processor Patent #: 4720780 InventorsAssigneeApplicationNo. 07/210754 filed on 06/23/1988US Classes:710/317, Crossbar708/404, Fast Fourier Transform (i.e., FFT)708/520, Matrix array708/522SystolicExaminersPrimary: Shaw, Gareth D.Assistant: Eakman, Christina M. Attorney, Agent or FirmInternational ClassesG06F 13/40 (20060101)G06F 17/50 (20060101) AbstractThe interconnection chip of the present invention is a custom chip which is designed to serve as an efficient link between system functional modules, such as arithmetic units, register files and input/output ports. The chip includes a crossbar interconnection, a FIFO or programmable delay for each of its inputs and a pipeline register file for each of its outputs. By using pre-stored control patterns, the chip can configure its crossbar and delays while performing other operations. Therefore, the usual functions of busses and register files can be realized with this single chip. Various embodiments and applications for the chip are disclosed.Other References
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