Automatic test system with enhanced performance of timing generators
January 28, 2007. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3718910 Programmable sequence generator for in-circuit digital testing IC Tester Programmable chip tester having plural pin unit buffers which each store sufficient test data for independent operations by each pin unit Self testing detection system for comparing digital signal transition times Adaptor circuit for adapting a test facility to a unit under test having a fast signal response System for automatic testing of circuits and systems Patent #: 4656632 InventorsAssigneeApplicationNo. 07/008030 filed on 01/28/1987US Classes:324/73.1, PLURAL, AUTOMATICALLY SEQUENTIAL TESTS702/125, Timing signal714/744, Clock or synchronization714/815Time delay/interval monitoredExaminersPrimary: Eisenzopf, Reinhard J.Assistant: Burns, W. Attorney, Agent or FirmInternational ClassesG01R 31/28 (20060101)G01R 31/319 (20060101) AbstractA unique automatic test system (100) is provided in which timing signals are generated in a novel manner as compared with prior art test systems. All adjustments for propagation delays of timing signals are made in a digital fashion, by adjusting the digital information which defines when an analog timing signal is to be generated. Deskewing of propagation delays is performed automatically under computer control, rather than by requiring careful adjustment of hardware deskewing elements. By adjusting for propagation skews digitally, propagation skews dependent on data values (logical 0 and logical 1) can be made. Furthermore, timing signals are provided by three timing edges, rather than by a timing pulse, thereby allowing more accurate generation of timing signals. The use of a complex switching matrix is eliminated by providing at least one timing generator per pin of the device under test, thereby eliminating complex hardware, propagation errors related to switching matrices, and providing enhanced capabilities for the user while simultaneously simplifying the problems associated with creating software used to control the test system during testing a device under test.Other References
| |
