High impendance-coupled CMOS SRAM for improved single event immunity
February 14, 2006. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3493786 Write speed-up circuit for integrated data memories Random access-erasable read only memory cell Radiation hard memory cell and array thereof Volatile/non-volatile logic latch circuit Integrated semiconductor memory array having improved logic latch circuitry Semiconductor memory operable as static RAM or EAROM Radiation hardened accessible memory Electronic circuits and structures employing enhancement and depletion type IGFETs Cross-coupled transistor memory cell for MOS random access memory of reduced power dissipation InventorsApplicationNo. 06/800990 filed on 11/22/1985US Classes:365/154, Flip-flop (electrical)257/297, With means for preventing charge leakage due to minority carrier generation (e.g., alpha generated soft error protection or "dark current" leakage protection)257/904, WITH PASSIVE COMPONENTS, (e.g., POLYSILICON RESISTORS)257/906, DRAM WITH CAPACITOR ELECTRODES USED FOR ACCESSING (E.G., BIT LINE IS CAPACITOR PLATE)365/156, Complementary365/190For complementary informationExaminersPrimary: Hecker, Stuart N.Assistant: Garcia, Alfonso Attorney, Agent or FirmInternational ClassesG11C 11/412 (20060101)G11C 5/00 (20060101) AbstractA CMOS SRAM exhibiting a high level of immunity to single event upset errors, such as caused by ionizing radiation, is disclosed. In CMOS SRAM cells with small feature sizes, single event errors result from ion interactions with transistor drains on the side of a cell holding a low voltage. The configuration of the cell presents a high impedance between these low voltage drains and the low voltage gate on the opposite side of the cell, while presenting a high impedance between corresponding components with high voltages. The SRAM cell is protected from single event errors while minimizing the increase in switching speed which accompanies any increase in internal cell impedance. | |
