Stacked static random access memory cell having capacitor
Patent 4805147 Issued on February 14, 1989. Estimated Expiration Date: 
June 9, 2006. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
June 9, 2006. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesField-effect transistor structure in multilevel polycrystalline silicon Semiconductor memory device Bipolar memory cell MOS static ram with capacitively loaded gates to prevent alpha soft errors Dynamic memory device with an RC circuit for inhibiting the effects of alpha particle radiation Patent #: 4641165 Inventors
AssigneeApplicationNo. 06/871994 filed on 06/09/1986US Classes:365/154, Flip-flop (electrical)257/297, With means for preventing charge leakage due to minority carrier generation (e.g., alpha generated soft error protection or "dark current" leakage protection)257/904, WITH PASSIVE COMPONENTS, (e.g., POLYSILICON RESISTORS)257/906, DRAM WITH CAPACITOR ELECTRODES USED FOR ACCESSING (E.G., BIT LINE IS CAPACITOR PLATE)257/E27.098, Static random access memory, SRAM, structure (EPO)257/E27.101, Load element being a resistor (EPO)365/182Insulated gate devicesExaminersPrimary: Hecker, Stuart N.Assistant: Bowler, Alyssa H. Attorney, Agent or FirmInternational ClassesG11C 11/412 (20060101)H01L 27/11 (20060101) Foreign Application Priority Data1985-06-10 JPAbstractA static random access memory cell in which capacitors are electrically connected to storage nodes, so that the memory cell will not suffer from soft error even when it is hit by alpha particles. The memory cell has MOS transistors, capacitors constituted by two polycrystalline silicon layers, and resistors constituted by a polycrystalline silicon layer, that are formed on a semiconductor substrate. | |
