U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Method of and arrangement for ordering of multiprocessor operations in a multiprocessor system with redundant resources

Patent 4805106 Issued on February 14, 1989. Estimated Expiration Date: Icon_subject July 9, 2007. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

3623014

3833798

3889237

Fuel control system
Patent #: 4015426
Issued on: 04/05/1977
Inventor: Hobo ,   et al.

Read request selection system for redundant storage
Patent #: 4187538
Issued on: 02/05/1980
Inventor: Douglas ,   et al.

System and method for accessing memory connected to different bus and requesting subsystem
Patent #: 4205373
Issued on: 05/27/1980
Inventor: Shah ,   et al.

Communication bus coupler
Patent #: 4257099
Issued on: 03/17/1981
Inventor: Appelt

Communications processor
Patent #: 4363094
Issued on: 12/07/1982
Inventor: Kaul ,   et al.

Arbitration controller providing for access of a common resource by a duplex plurality of central processing units
Patent #: 4363096
Issued on: 12/07/1982
Inventor: Comfort ,   et al.

Logic system for selectively reconfiguring an intersystem communication link
Patent #: 4370708
Issued on: 01/25/1983
Inventor: Bruce ,   et al.

More ...

Inventor

Application

No. 07/073400 filed on 07/09/1987

US Classes:

710/200, ACCESS LOCKING711/152Memory access blocking

Examiners

Primary: Harkcom, Gary V.
Assistant: Anderson, Lawrence E.

Attorney, Agent or Firm

International Classes

G06F 11/14 (20060101)
G06F 11/16 (20060101)

Abstract

To lock use of shared information to itself in a multiprocessor system (100) having two independently and asynchronously operating processors (101, 111) whose main store units (102, 112) duplicate each other's contents, a processor must cause an atomic read-modify-write (RMW) operation to be executed on a semaphore in the duplicated main store units of both processors. To properly order execution of multiple such RMW operations, arbiters (106, 116) of system buses (105, 115) of the two processors communicate over an interarbiter channel (121). The arbiter of a source processor that wishes to perform an RMW operation notifies the other processor's arbiter over the interarbiter channel. Simultaneous attempts at notification by both arbiters are resolved in favor of one of them that is designated the master. The notifying arbiter prevents its processor from performing another RMW operation until the one RMW operation has completed thereon, but permits other operations to proceed normally. The notified arbiter prevents its processor from performing another RMW operation until the one RMW operation has been transferred via interprocessor links (107, 117) and bus (120) from the source processor to the notified arbiter's processor and has been performed thereon, but permits other operations to proceed normally. Thus multiple RMW operations are performed on both processors in the same order asynchronously and without impacting performance of other operations.

Other References

  • IBM "System/370 Principles of Operation", pp. 7-12 to 14 and 7-39
  • I. K. Hetherington et al., "3B20D Processor Memory Systems", The Bell System Technical Journal, V. 62, No. 1, (1-1983), pp. 207-220
  • Y. Lee et al., "Design and Evaluation of a Fault-Tolerant Multiprocessor Using Hardware Recovery Blocks", IEEE Transactions on Computers, V. C-33, No. 2 (2-1984), pp. 113-124
  • T. Hirota et al., "Computer-Aided Design of Software Module: Validity of Concurrent Processing on On-Line File", Proceedings of 3d U.S.A.-JAPAN Computer Conference, (10-12 Oct. 1978, NY), pp. 220-224
  • N. T. Christensen, "Programmable Priority Mechanism" IBM Technical Disclosure Bulletin, vol. 17, No. 7 (12-74)
  • Z. Kohavi, Switching and Finite Automata Theory, (2d ed.), McGraw-Hill, 1978, Ch. 9
  • J. Klir and L. Seidl, Synthesis of Switching Circuits, Gordon and Breach Science Pubs., 1968, pp. 203-205
  • M. Mano, Computer Logic Design, Prentice-Hall, Inc., 1972, Ch. 7
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