Bit-line isolated, CMOS sense amplifier
July 28, 2007. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMonolithically integrated semiconductor memory Sense amplifier Semiconductor memory device having active pull-up circuits Sense amplifier for CMOS semiconductor memory devices having symmetrically balanced layout ECL to FET interface circuit for field effect transistor arrays Midpoint sense amplification scheme for a CMOS DRAM CMOS sense amplifier with isolated sensing nodes Patent #: 4716320 InventorAssigneeApplicationNo. 07/078746 filed on 07/28/1987US Classes:327/54, Having feedback327/57, With latching type element (e.g., flip-flop, etc.)365/190, For complementary information365/203, Precharge365/205Flip-flop used for sensingExaminersPrimary: Hudspeth, DavidAttorney, Agent or FirmInternational ClassesG11C 7/00 (20060101)G11C 7/06 (20060101) G11C 7/12 (20060101) AbstractA sense amplifier includes a pair of decoupling transistors (P4, P5) for isolating the sense nodes (X, Y) from the bit lines (B, B) during the assertion of a sense signal, thereby eliminating the occurrence of current spikes and increasing its gain. | |
