Dual port memory controller
Patent 4796232 Issued on January 3, 1989. Estimated Expiration Date: 
October 20, 2007. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
October 20, 2007. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesSerial accessed semiconductor memory with reconfigureable shift registers Patent #: 4683555 InventorAssigneeApplicationNo. 07/111428 filed on 10/20/1987US Classes:365/189.03, Plural use of terminal365/219, SiPo/PiSo365/222, Data refresh365/230.03, Plural blocks or banks365/230.05Multiple port accessExaminersPrimary: Fears, Terrell W.Attorney, Agent or FirmInternational ClassesG06F 13/18 (20060101)G06F 13/16 (20060101) G11C 8/12 (20060101) G11C 8/00 (20060101) G11C 11/406 (20060101) G11C 8/16 (20060101) AbstractA dual port memory controller is operative to interface a pair of processors to a common multiple bank organized memory. A dedicated logic array provides arbitration between conflicting processor requests for memory access. Refresh means are operative upon the memory banks in a staggered fashion to minimize noise created within the system during refresh and to permit simultaneous refresh of an access to the memory. | |
