Process for formation of shallow silicided junctions

Patent 4788160 Issued on November 29, 1988. Estimated Expiration Date:

March 31, 2007. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

High speed lateral bipolar transistor
Patent #: 4259680
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Issued on: 07/01/1986
Inventor: Tsang

Inventors

Assignee

Texas Instruments Incorporated

Application

No. 07/032836 filed on 03/31/1987

US Classes:

438/305, Plural doping steps257/382, With contact to source or drain region of refractory material (e.g., polysilicon, tungsten, or silicide)257/383, Contact of refractory or platinum group metal (e.g., molybdenum, tungsten, or titanium)257/388, Gate electrode consists of refractory or platinum group metal or silicide257/E21.337, Through-implantation (EPO)257/E29.146, On silicon (EPO)438/306, Plural doping steps438/526, Forming buried region438/533, And contact formation (i.e., metallization)438/586, Combined with formation of ohmic contact to semiconductor region438/923Diffusion through a layer

Examiners

Primary: Hearn, Brian E.
Assistant: Quach, T. N.

Attorney, Agent or Firm

International Classes

H01L 21/265 (20060101)
H01L 21/336 (20060101)
H01L 21/02 (20060101)
H01L 29/40 (20060101)
H01L 29/45 (20060101)

Abstract

A process for forming shallow silicided junctions includes the step of sputtering a layer of titanium (28) over a moat region to cover a gate electrode (18) and a sidewall oxide (22) formed on the sidewalls of the gate electrode (18). The titanium is reacted with exposed silicon regions (24) and (26) to form silicide layers (30) and (32) and then dopant impurities are implanted into the substrate (10) prior to stripping the unreacted titanium. The unreacted titanium (36), (38), or (40) functions as a mask to both offset the implanted regions from the channel region (20) under the gate electrode (18) and also to prevent impurities from entering the substrate at regions outside the defined moat region.