Adaptive instruction processing by array processor having processor identification and data dependent status registers in each processing element
Patent 4783738 Issued on November 8, 1988. Estimated Expiration Date: 
March 13, 2006. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
March 13, 2006. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3287702 3287703 3544973 Cooperative-word linear array parallel processor Pipelined data processing system with centralized microprogram control Array processor with parallel operations per instruction Bit enable circuitry for an image analyzer system Partitionable parallel processor Massively parallel processor computer Image analyzer with common data/instruction bus InventorsApplicationNo. 06/839311 filed on 03/13/1986US Classes:712/21, Multiple instruction, Multiple data (MIMD)712/13, Partitioning712/15, Reconfiguring712/226Instruction modification based on conditionExaminersPrimary: Shaw, Gareth D.Assistant: Fairbanks, Jonathan C. Attorney, Agent or FirmInternational ClassesG06F 9/44 (20060101)G06F 15/76 (20060101) G06F 15/80 (20060101) F02B 75/02 (20060101) AbstractEquipping individual processing elements with an instruction adapter provides an array processor with adaptive spatial-dependent and data-dependent processing capability. The instruction becomes variable, at the processing element level, in response to spatial and data parameters of the data stream. An array processor can be optimized, for example, to carry out very different instructions on spatial-dependent data such as blank margin surrounding the black lines of a sketch. Similarly, the array processor can be optimized for data-dependent values, for example to execute different instructions for positive data values than for negative data values. Providing each processing element with a processor identification register permits an easy setup by flowing the setup values to the individual processing elements, together with setup of condition control values. Each individual adaptive processing element responds to the composite values of original setup and of the data stream to derive the instruction for execution during the cycle. In the usual operation, each adaptive processing element is individually addressed to set up a base instruction; it also is conditionally set up to execute a derived instruction instead of the base instruction. An array processor made up of adaptive processing elements can adapt dynamically to changes in its input data stream, and thus can be dynamically optimized, resulting in greatly enhanced performance at very low incremental cost.Other References
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